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← All SystemsSystem 06 / packagingReviewed Aug 29, 2026

Packaging & Memory

Chiplets, HBM, interposers, substrates, bonding, and test now decide how much fabricated silicon becomes usable AI compute.

Understand the system

How it works

Advanced packaging and HBM are no longer back-end details; they are co-equal performance, yield, and capacity constraints for accelerators.

Integration dependencies

Bringing memory and packaging together

Select a capability to explore its role and connections.

Selected: Memory fabrication

Memory fabrication

DRAM and NAND fabs produce memory dies whose capacity, yield, and qualification constrain accelerators, servers, and storage.

Explore Memory fabrication in Atlas

Documented connections

Selected documented dependencies. Arrows retain their Atlas direction; they do not represent quantities or a complete engineering process.

AI accelerators are assembled systems rather than solitary dies. Logic chiplets and stacks of high-bandwidth memory must be joined through dense interconnects, interposers, bridges, substrates, micro-bumps, thermal interfaces, and precise bonding. Package warpage, known-good-die strategy, test coverage, substrate supply, and stack yield all decide whether expensive wafers become reliable modules.

Why chiplets need packaging

Partitioning a system across dies can improve reticle economics and mix process technologies, but it transfers complexity into die-to-die links, assembly, power delivery, thermals, and test.

  • Chiplet benefits arrive with package-level penalties
  • Failure domains cross the complete assembly
Supporting evidence · 3
  1. [1] TSMC's CoWoS platform integrates logic chiplets and high-bandwidth memory on an interposer within an advanced package.
  2. [2] Inspection, metrology, and data analysis form a feedback loop used to detect defects and control semiconductor yield.
  3. [3] UCIe 2.0 supports a 32 GT/s maximum data-rate option, while UCIe 3.0 adds 48 GT/s and 64 GT/s options; these are protocol specifications rather than delivered application throughput.

HBM is vertical memory

DRAM dies are thinned, stacked, connected with through-silicon vias, and placed near logic to provide much higher bandwidth than conventional off-package memory channels.

  • Shorter memory distance enables higher bandwidth
  • Capacity, stack height, and thermal load move together
Supporting evidence · 2
  1. [1] Micron specifies more than 1.2 TB/s of memory bandwidth per HBM3E stack.
  2. [2] Micron lists HBM3E configurations of 24 GB in an eight-high stack and 36 GB in a twelve-high stack.

Assembly yield compounds

A package can contain several costly known-good components. Bonding defects, warpage, substrate issues, or one failed stack can strand value accumulated through many upstream steps.

  • Model yield across every component and bond
  • Include rework and test escape costs
Supporting evidence · 2
  1. [1] Leading-edge wafers pass through thousands of fabrication process steps over a period measured in weeks before packaging and test.
  2. [2] TSMC's CoWoS platform integrates logic chiplets and high-bandwidth memory on an interposer within an advanced package.

Thermals start in the package

Heat flux, power delivery, signal integrity, and mechanical stress are established before a module reaches a server. Rack cooling cannot compensate for every package-level limitation.

  • Link package heat paths to cold plates
  • Connect memory placement to accelerator utilization
Supporting evidence · 2
  1. [1] NVIDIA specifies 141 GB of HBM3E capacity and 4.8 TB/s of memory bandwidth for the H200 accelerator.
  2. [2] NVIDIA's DGX GB200 documentation describes a rack-scale system with 72 GPUs, 36 Grace CPUs, and an approximately 120 kW power envelope, with liquid cooling alongside air-cooled components.

Featured evidence

Documented capacity for two unlike HBM configurations

Capacity per stack for a Micron HBM3E eight-high specification and an SK hynix HBM4 twelve-high customer sample.
Documented capacityGB per stack
View chart values
Documented capacity for two unlike HBM configurations — underlying values in GB per stack
CategoryDocumented capacity
Micron HBM3E 8-high24 GB per stack
SK hynix HBM4 12-high sample36 GB per stack

NOT LIKE-FOR-LIKE — different generations and stack heights; the 36 GB HBM4 figure was sample status, not evidence of volume production or availability.

Key indicators

Key measures & constraints

  1. 01

    TSMC's CoWoS platform integrates logic chiplets and high-bandwidth memory on an interposer within an advanced package.

    Class
    vendor claim
    Geography
    Global
    Period
    2025 platform portfolio
    Confidence
    high
    Trace evidence
  2. 02

    Micron specifies more than 1.2 TB/s of memory bandwidth per HBM3E stack.

    Class
    vendor spec
    Geography
    Global
    Period
    HBM3E product generation
    Confidence
    high
    Trace evidence
  3. 03

    UCIe 2.0 supports a 32 GT/s maximum data-rate option, while UCIe 3.0 adds 48 GT/s and 64 GT/s options; these are protocol specifications rather than delivered application throughput.

    Class
    fact
    Geography
    Global
    Period
    UCIe 2.0 released 2024 and UCIe 3.0 released 2025
    Confidence
    high
    Trace evidence
  4. 04

    SK hynix described its March 2025 12-layer HBM4 customer sample as a 36 GB stack; the announcement documented sample and certification status rather than qualified volume production.

    Class
    vendor claim
    Geography
    Global
    Period
    March 2025
    Confidence
    medium
    Trace evidence

System map

Connections across the system

Explore inputs, outputs, and shared capabilities in the Atlas. Open the register for every documented relationship.

Across the system boundary Selected documented relationships · arrows follow the Atlas

Enters this system 4

  1. Yield learning→ Advanced packagingTrace relationship
  2. Memory fabrication→ High-bandwidth memoryTrace relationship

Leaves this system 3

  1. AI accelerator← Advanced packagingTrace relationship
  2. AI accelerator← High-bandwidth memoryTrace relationship
System 06Packaging & Memory5 internal relationships

Shared capabilities can belong to more than one System. These links carry materials, energy, information, capital, or permissions; they describe dependencies, not quantities or a complete process model.

Explore 6 capabilities and operating boundaries
Atlas nodes / 6
All documented relationships · 12
  1. criticalinput
    Yield learningAdvanced packaging

    Known-good logic dies enter high-value package assembly.

    Trace relationship
    Supporting evidence · 2
    1. [1] TSMC's CoWoS platform integrates logic chiplets and high-bandwidth memory on an interposer within an advanced package.
    2. [2] Inspection, metrology, and data analysis form a feedback loop used to detect defects and control semiconductor yield.
  2. criticalinternal
    High-bandwidth memoryAdvanced packaging

    Qualified HBM stacks are bonded beside logic in advanced packages.

    Trace relationship
    Supporting evidence · 2
    1. [1] Micron specifies more than 1.2 TB/s of memory bandwidth per HBM3E stack.
    2. [2] TSMC's CoWoS platform integrates logic chiplets and high-bandwidth memory on an interposer within an advanced package.
  3. criticaloutput
    Advanced packagingAI accelerator

    Assembly and test turn logic and HBM into a qualified accelerator module.

    Trace relationship
    Supporting evidence · 2
    1. [1] TSMC's CoWoS platform integrates logic chiplets and high-bandwidth memory on an interposer within an advanced package.
    2. [2] NVIDIA specifies 141 GB of HBM3E capacity and 4.8 TB/s of memory bandwidth for the H200 accelerator.
  4. criticaloutput
    High-bandwidth memoryAI accelerator

    Memory capacity and bandwidth bound accelerator workload performance.

    Trace relationship
    Supporting evidence · 2
    1. [1] Micron specifies more than 1.2 TB/s of memory bandwidth per HBM3E stack.
    2. [2] NVIDIA specifies 141 GB of HBM3E capacity and 4.8 TB/s of memory bandwidth for the H200 accelerator.
  5. criticalinput
    Memory fabricationHigh-bandwidth memory

    Qualified DRAM dies from memory fabs become the active layers of HBM stacks.

    Trace relationship
    Supporting evidence · 2
    1. [1] SK hynix described its March 2025 12-layer HBM4 customer sample as a 36 GB stack; the announcement documented sample and certification status rather than qualified volume production.
    2. [2] Micron lists HBM3E configurations of 24 GB in an eight-high stack and 36 GB in a twelve-high stack.
  6. criticalinput
    Package substratesAdvanced packaging

    Advanced packages require compatible high-density substrates for power, signal, and mechanical integration.

    Trace relationship
    Supporting evidence · 2
    1. [1] TSMC's CoWoS platform integrates logic chiplets and high-bandwidth memory on an interposer within an advanced package.
    2. [2] SIA's high-level semiconductor value chain runs from research and development through chip design, front-end wafer fabrication, back-end assembly, test and packaging, and finally circuit-board integration into products.
  7. criticaloutput
    Package test & qualificationAI accelerator

    Final qualification determines whether integrated accelerator packages can enter systems.

    Trace relationship
    Supporting evidence · 2
    1. [1] NVIDIA documents a maximum of 64 framebuffer page retirements for legacy GPUs and up to 512 framebuffer row-remapping entries for Ampere and later generations.
    2. [2] SIA's high-level semiconductor value chain runs from research and development through chip design, front-end wafer fabrication, back-end assembly, test and packaging, and finally circuit-board integration into products.
  8. importantinput
    Export controlsHigh-bandwidth memory

    Export rules can restrict advanced memory products and related technology.

    Trace relationship
    Supporting evidence · 1
    1. [1] The December 2024 U.S. package added controls on 24 categories of semiconductor manufacturing equipment, three software-tool categories, and HBM, plus 140 Entity List additions.
  9. importantinternal
    Assembly, test & OSATAdvanced packaging

    Assembly, test & OSAT supplies a distinct operating capability within its broader Atlas system.

    Trace relationship
    Supporting evidence · 2
    1. [1] SIA's high-level semiconductor value chain runs from research and development through chip design, front-end wafer fabrication, back-end assembly, test and packaging, and finally circuit-board integration into products.
    2. [2] Semiconductor design, equipment, materials, wafer fabrication, and assembly remain distributed across highly specialized regional clusters.
  10. importantinternal
    Interposers & TSVsAdvanced packaging

    Interposers & TSVs supplies a distinct operating capability within its broader Atlas system.

    Trace relationship
    Supporting evidence · 2
    1. [1] TSMC's CoWoS platform integrates logic chiplets and high-bandwidth memory on an interposer within an advanced package.
    2. [2] UCIe 2.0 supports a 32 GT/s maximum data-rate option, while UCIe 3.0 adds 48 GT/s and 64 GT/s options; these are protocol specifications rather than delivered application throughput.
  11. importantinternal
    Hybrid bondingAdvanced packaging

    Hybrid bonding supplies a distinct operating capability within its broader Atlas system.

    Trace relationship
    Supporting evidence · 2
    1. [1] NIST's advanced-packaging research program identified roughly 100 million design instances as the point above which then-current EDA abstractions made full-chip implementation impractical, forcing designs to be partitioned into blocks.
    2. [2] TSMC's CoWoS platform integrates logic chiplets and high-bandwidth memory on an interposer within an advanced package.
  12. importantinternal
    Package test & qualificationAdvanced packaging

    Package test & qualification supplies a distinct operating capability within its broader Atlas system.

    Trace relationship
    Supporting evidence · 2
    1. [1] NVIDIA documents a maximum of 64 framebuffer page retirements for legacy GPUs and up to 512 framebuffer row-remapping entries for Ampere and later generations.
    2. [2] SIA's high-level semiconductor value chain runs from research and development through chip design, front-end wafer fabrication, back-end assembly, test and packaging, and finally circuit-board integration into products.

Named companies + institutions

Organizations & their roles

  1. material · public company

    Intel

    Intel Corporation

    Integrated semiconductor company spanning processor design, fabrication, packaging, systems, and foundry services.

    Roles, locations & evidence
    Role
    manufacturer
    Products / service
    Advanced package integration · Semiconductor assembly and test
    Documented activity
    World · Malaysia · Vietnam
    Headquarters
    United States
    Why this organization belongs in the System
    • Advanced packaging

      Intel's filing-backed operating portfolio includes advanced package integration; no subregional operating place is asserted, and headquarters is not used as a proxy. Representative status does not imply market rank.

    • Package test & qualification

      Intel's maintained manufacturing-site documentation directly lists assembly-and-test sites in both countries. Principal status is withheld because this edition does not close a concentration, capacity, shipment, revenue, or installed-base measure for the role.

  2. material · public company

    Micron

    Micron Technology, Inc.

    Memory and storage manufacturer supplying DRAM, HBM, NAND, and related products for AI systems.

    Roles, locations & evidence
    Role
    manufacturer
    Products / service
    DRAM and NAND assembly, test, marking, and packaging · High-bandwidth memory · HBM advanced-packaging facility under construction
    Documented activity
    India · World · Singapore
    Headquarters
    Boise
    Why this organization belongs in the System
    • Package test & qualification

      Micron and the Government of India directly confirm commercial production at the Sanand assembly-and-test facility.

    • High-bandwidth memory

      Micron's filing-backed operating portfolio includes high-bandwidth memory; no subregional operating place is asserted, and headquarters is not used as a proxy. Representative status does not imply market rank.

    • High-bandwidth memory

      Micron's project updates directly locate the HBM packaging buildout in Singapore and retain its contribution as future, not operating, capacity.

  3. representative · public company

    Amkor

    Amkor Technology, Inc.

    Outsourced semiconductor assembly and test provider spanning advanced packaging, package test, and related services.

    Roles, locations & evidence
    Role
    manufacturer
    Products / service
    Advanced packaging services · Outsourced assembly and test · Outsourced semiconductor assembly and packaging · Package test services · Wafer probe and package-test services
    Documented activity
    World · Asia · United States · Vietnam · Philippines
    Headquarters
    United States
    Why this organization belongs in the System
    • Advanced packaging

      Amkor's filing-backed operating portfolio includes advanced packaging services; no subregional operating place is asserted, and headquarters is not used as a proxy. Representative status does not imply market rank.

    • Assembly, test & OSAT

      Amkor's filing-backed operating portfolio includes outsourced assembly and test; the listed places are explicit role geographies, and headquarters is not used as a proxy. Representative status does not imply market rank.

    • Assembly, test & OSAT

      Amkor's maintained service directory directly identifies assembly and packaging operations in Vietnam and the Philippines. Principal status is withheld because this edition does not close a concentration, capacity, shipment, revenue, or installed-base measure for the role.

    • Package test & qualification

      Amkor's filing-backed operating portfolio includes package test services; no subregional operating place is asserted, and headquarters is not used as a proxy. Representative status does not imply market rank.

    • Package test & qualification

      Amkor's maintained service directory directly identifies test functions at its Vietnam and Philippine facilities. Principal status is withheld because this edition does not close a concentration, capacity, shipment, revenue, or installed-base measure for the role.

  4. representative · public company

    ASE Technology

    ASE Technology Holding Co., Ltd.

    Taiwan-based semiconductor assembly, packaging, testing, materials, and electronic manufacturing-services group.

    Roles, locations & evidence
    Role
    manufacturer
    Products / service
    Advanced packaging · Advanced semiconductor packaging · Assembly and test services · Semiconductor test · Semiconductor package testing
    Documented activity
    Taiwan · Malaysia · Asia
    Headquarters
    Taiwan
    Why this organization belongs in the System
    • Advanced packaging

      ASE Technology's filing-backed operating portfolio includes advanced packaging; the listed places are explicit role geographies, and headquarters is not used as a proxy. Representative status does not imply market rank.

    • Advanced packaging

      ASE's official fifth-plant launch identifies advanced-packaging manufacturing at its Penang site. Principal status is withheld because this edition does not close a concentration, capacity, shipment, revenue, or installed-base measure for the role.

    • Assembly, test & OSAT

      ASE Technology's filing-backed operating portfolio includes assembly and test services; the listed places are explicit role geographies, and headquarters is not used as a proxy. Representative status does not imply market rank.

    • Package test & qualification

      ASE Technology's filing-backed operating portfolio includes semiconductor test; the listed places are explicit role geographies, and headquarters is not used as a proxy. Representative status does not imply market rank.

    • Package test & qualification

      ASE's official fifth-plant launch identifies packaging-and-test operations at its Penang site. Principal status is withheld because this edition does not close a concentration, capacity, shipment, revenue, or installed-base measure for the role.

All other organizations · 1
  1. representative · public company

    TSMC

    Taiwan Semiconductor Manufacturing Company Limited

    Dedicated semiconductor foundry supplying advanced and specialty wafer fabrication and advanced packaging services.

    Roles, locations & evidence
    Role
    manufacturer
    Products / service
    CoWoS and 3DFabric integration
    Documented activity
    Taiwan
    Headquarters
    Taiwan
    Why this organization belongs in the System
    • Advanced packaging

      TSMC's filing-backed operating portfolio includes cowos and 3dfabric integration; the listed places are explicit role geographies, and headquarters is not used as a proxy. Representative status does not imply market rank.

Affected policies

Relevant policies

Legal status is separated from policy objective. Every record keeps its jurisdiction, mechanism, affected nodes, and verification date.

  1. effective

    U.S. CHIPS and Science Act incentives

    Expand domestic semiconductor manufacturing, research, workforce, and supply-chain resilience.

    Mechanism, scope & sources

    Manufacturing grants, loans and guarantees, research programs, and an investment tax credit with program conditions; current project records distinguish proposed and final awards, with disbursement tied to milestones.

    United StatesOpen full policy record
  2. effective

    Advanced-semiconductor export controls, as amended

    Restrict specified capabilities used to produce advanced semiconductors and advanced computing systems in China.

    Mechanism, scope & sources

    Combines controlled equipment, software, HBM, entity, end-use, and license requirements with later transaction-specific exceptions and case-by-case review policies in the current EAR framework.

    United States export administrationOpen full policy record

Read this System in the field guide

Continue in the Volumes

Start with three selected readings, or explore the complete reading list.

Start here
  1. 01
    Volume III · PackageChiplets and partitioning
  2. 02
    Volume III · PackageCapacity and bandwidth
  3. 03
    Volume III · PackageInspection, test, and qualification
Complete reading list
Volume III

Package

14 spreads
  1. III · 01A new system boundary
  2. III · 02Chiplets and partitioning
  3. III · 03Interposers, redistribution, and substrates
  4. III · 04The memory hierarchy
  5. III · 05How HBM is assembled
  6. III · 06Capacity and bandwidth
  7. III · 07Power and heat begin in the package
  8. III · 08Known-good die
  9. III · 09The assembly sequence
  10. III · 10Bonding and mechanical control
  11. III · 11Inspection, test, and qualification
  12. III · 12Capacity is a matched set
  13. III · 13Qualification and change control
  14. III · 14From package to module
Related cross-System reading · 9 spreads

Evidence & review

currentEvidence health25 active claims · next review Oct 13, 2026
Active claims
25
Sources
32
High volatility
4
Next review
Oct 13, 2026
Due soon
0
Overdue
0
Superseded
0
Open complete evidence ledger

Behind the claim

Evidence, in context.

Opening the evidence record…